Research On The Key Technology Of Graphic Processor And The Parallel Structure Of Ray Tracing

With the development of computer graphics and integrated circuit technology, the research on Graphics Processing Unit(GPU) has made great progress. The architecture of GPUs has developed from the fixed function pipeline architecture to the large scale parallel unified shader architecture. However, modern GPUs still are based on the rasterization, which are fast and suit for real-time processing, but are difficult to achieve the effect of complex global illumination. The ray tracing algorithms can achieve superior visual effects, but the computations of these algorithms are very expensive and could not be processed in real time on modern GPUs. Hence it is very important to study innovative algorithms and architectures of GPU.In order to optimize a GPU’s computational efficiencies, this paper proposes a parallel architecture for a fixed pipeline GPU which has been fabricated on 130 nm CMOS technology. And the paper presents a 2-dimension parallel array architecture to speed up the ray tracing which was fabricated on 130 nm CMOS technology. A KDTree parallel structure and a parallel algorithm for interactive medical image segmentation are implemented on the architecture. A supersampling anti-aliasing algorithm is implemented on the rasterization pipeline and the ray tracing pipeline. The main contributions of the paper as follows:Based on the analysis of the fixed function pipeline architecture, an optimized parallel architecture for GPU is proposed. The architecture adopts the rasterization algorithm and designs multiple pipelines which have the configurable parallel vertex shaders, pixel shaders and scan units. A Clock-based simulation platform is implemented and a chip using 0.13μm CMOS technology has been fabricated.To speed up the ray tracing algorithms, a configurable array architecture(Ray Tracing GPU, RTGPU) is proposed, and a ray tracing pipeline is mapped onto the RTGPU. RTGPU is composed of some parallel ray tracing cores(RTCore) and each RTCore is a 16*16 processing units(PE) array, in which the connections between PE are wired by short line. A RTCore is controlled by 16 row controllers for function configuration and 16 column controllers for data manipulation. Data exchanges could be occurred between the adjacent PEs by shared memory or among remote PEs by routers. The simulation results and a chip validate the correctness of the design.A supersampling anti-aliasing algorithm is proposed to reduce the redundant sampling points. Based on the recursive method, the fragments in the edge region are subdivided to get superior visual effects and the fragments in the non-edge region are not subdivided. The color of midpoint substitutes the color of region. The algorithm is implemented on the rasterization pipeline and the ray tracing pipeline. The experiments show that the effect of the algorithm has the same as the MSAA, but the numbers of sampling point are reduced and the computational efficiency is improved.Based on the architecture of RTGPU, a parallel KDTree algorithm is implemented. The SAH is used to calculate the cost function; the maximum projection is used to determine the split axis; the index of graphic element is used to substitute the structure of the primitive, which reduces the amount of data movement. The simulation demonstrates that the efficiency of building KDTree is improved greatly.Based on the RTGPU architecture proposed in this paper, a region segmentation algorithm for interactive medical image is parallelized. Simulation results show that a high speedup is obtained by mapping the algorithm onto the RTGPU architecture.