Bitstream Resolving And Circuit Recovering Of FPGA

As the high-speed development of electronic technology andcomputer technology since1990s, Reconfigurable Computing (RC) isbecoming a hot researching domain. Field Programmable Gate Array(FPGA) is one of the important objects, for its reconfigurable feature. A lotof remarkable RC results come out of FPGA, at architecture, modeling andalgorithm topic. However, most of such research is confined to theElectronic Design Automation (EDA) tools, supplied by FPGAmanufacturers, which can only allow researchers do RC research onmodule or system level, not bit level. Meanwhile, because every work hasto strictly obey the developing flow of EDA tools, some ideas of real-timeRC and Partial Dynamic Reconfiguration exist on theory finally. Real-timeand bit level reconfiguration work on FPGA comes to reality only if thewhole mapping relationship between bitstream file and transistors in FPGAchip is obtained.After researching the materials of FPGA and ISE tools of Xilinx Inc.,we design and implement a set of integrated and high efficient methods toresolve their relationship, and generate a mapping database, includingmethod for analyzing relationship between single Programmable Point (PP)and bitstream data, method for offset formula, and method for bitstream analyzing based on distributed architecture. By experiments verifying, theresolving methods are suitable for all FPGA series of Xilinx Inc., and themapping data has high accuracy.Besides, based on the mapping database, we develop BIT2NCD tool,which could reverse the bitstream file to Native Circuit Description (NCD)netlist file. By comparing the original circuit with recovering circuit, itproves the correctness and integrality of mapping data.