Design And VLSI Implementation Of High Efficient Hybrid Floating-point FFT Accelerator

Fast Fourier Transform (FFT) is one of the most commonly used digital signal processing algorithms. It is always a hot topic in the field of digital signal processing. Nowadays, FFT is the key operation for many emerging applications, such as orthogonal frequency division multiplexing (OFDM) based handheld mobile communication device and biomedical signal processing platform. These applications have a significant thing in common, that is, the power consumption of entire system must be very low in order to extend the product’s life cycle. Meanwhile, good adaptability is also required in the system. When facing with various signal inputs, the system should still produce the desired results. Therefore, the FFT accelerator is required to achieve high energy efficiency, low cost and high flexibility under the premise of sound Signal to Quantization Noise Ratio (SQNR) performance.According to these requirements, this thesis designs and optimizes a FFT accelerator from the perspective of algorithm and circuit. In terms of the algorithm, this thesis summarizes the data representation formats of FFT hardware implementation, including fixed-point format, floating-point format and fixed-point based scaling method. On the basis of these formats, this thesis proposes a dynamic bias adjusting hybrid floating-point method. The method adoptes the exponent field of floating-point format and the fraction field of fixed-point format. The real part and the imaginary part of a complex number share a common exponent field. This can reduce the hardware cost and power consumption under the premise of sufficient data accuracy. Furthermore, the dynamic bias adjusting method can dynamically adjust the numeric range of the data format during the arithmetic operations in face of different input signals, so that the overall SQNR is improved. This mechanism provides the flexibility and precision of FFT accelerator. Therefore, using dynamic bias adjusting hybrid floating-point method can obtained high SQNR with small data bit-width, so as to achieve the goal of low power consumption and low cost.In the circuit level, this thesis implements the FFT accelerator by using a single memory structure to reduce the hardware cost. In the data path, this thesis introduces a variety of methods to lower the power consumption and improve the SQNR. First, this thesis analyzes and reduces the number of normalization operation in the butterfly unit from fifteen down to four. Second, this thesis analyzes and shortens the internal bit-width in the butterfly unit. If the bit-width of fraction field is 9, then up to 6 bits can be shortened. Third, Trounding strategy is used to reduce quantization error as much as possible without adding too much hardware overhead. Finally, this thesis focuses on the design of FFT accelerator based on the low-voltage memory. An overview of the type of memory failure is summerized. Then the analysis and simulation methods of memory failure rate under certain voltage is described. Thereafter, the relationship between the failure rate and a specific circuit voltage for a certain frequency is presented. According to the relationship, the SQNR and power reduction of FFT accelerator is calculated under different memory voltage.Our FFT accelerator can perform 64～ 8192-point transformation. The data bit-width is 3+2*9 bit. The memory voltage is 0.7V. When using SMIC 65nm technology, the FFT accelerator can run at 400MHz. The area is 0.482mm2 and the power consumption is 35.3mW. The SQNR of 64-point and 8192-point is 41.6 dB and 35.8 dB respectively.