Design Of A Lossless JPEG Compression Circuit

JPEG-LS is the standard of still image lossless compression. There is no information loss in the process of compression.The image can be completely restored to the source image. The average compression ratio of JPEG-LS is about 2:1.The JPEG-LS technology has been widely used in the high image quality demanding fields such as satellite remote sensing and medical tests. This thesis uses the JPEG-LS hardware encoding circuit with low power on the fields of medical tests.The JPEG-LS hardware design can be divided into memory module, normal encoding module, run-length coding module, Golomb encoding modules. The encoding circuit firstly store image into the local RAM through the memory interface. The normal encoding module calculate the prediction error of the current pixel according to the current pixel and its context pixels. The run-length encoding module switch between the "scan run"state and "disruption of run"state according to whether the real pixel values and estimated pixel values are equal. The module calculate the length of run-length scanning and run-length encoding interruption pixel values. Golomb encoding module divide the prediction error, and the quotient is one-hot encoded, the remainder is binary encoded.In the thesis,the design refer to LOCO-I algorithm.The hardware circuit is designed by Verilog.With the same image data as input, we can compare the output of the software and hardware to confirm the correctness of the function. In the SMIC180nm process, the JPEG-LS circuit is synthesised and the equivalent logic gate is 37443. In the test set of multiple images, the average compression rate of encoding circuit is 2:1, the average compression time is 26ms, and the average power consumption is 5.5mW in 40MHz clock frequency.