Study Of System-level Modeling Technology For Network-on-Chip Based Many-core Processor

Multi-core or many-core architecture using Network on Chip (NoC)technology has the advantage of parallel computing and high throughoutcommunication performance. But at the same time it brings more complexity ofexploring the hardware and software design space. In order to get a betterunderstanding of system level design issues of NoC based many-core architecture,we first design the cycle accurate system-level models of NoC in both signal level(or called Register Transfer Level) and transactional level. And then we optimizethe modeling method to improve the simulation speed for the many-corearchitecture that can integrate hundreds of cores. Finally we developed a many-core simulator that integrates both of the NoC model and an ARM compatibleinstruction simulator. The main contribution of this paper is as follows：Firstly, we developed a cycle-accurate RTL level to explore the design spaceof an improved packet-connected circuit NoC. Through qualitative analysis, wethen proposed an optimizing method by reducing the module hierarchy levels,reconstructing the process relationship and virtualizing the switch architecture.Experiments with "Full" load show that the optimized RTL model has goodscalability and the simulation time is reduced by an average of48%than RTLmodel.Secondly, we developed a cycle-accurate transaction-level model to improveboth of the simulation efficiency and NoC performance. Implicit state machine andevent-driven are used to complete the routing node model, and automaticinterconnection algorithm is used to generate network automatically."Full" loadtest results show that the simulation time cost by transaction-level model isreduced by an average of53%than optimized RTL model.Finally, we implemented the many-core processor system-level simulationplatform integrated by ARM-SoC and NoC with the cycle acurate transaction levelmodeling technology. ARM instruction set model is packaged with SystemC asprocessor model. The master interface, resource network interface and DMA model are designed based on an open-source transaction-level AHB bus. The ARM-SoCsystem is composed of processor, master interface, AHB bus and other slavedevices. Then the MPSoC-NoC system-level simulation platform is integrated byARM-SoC and transaction-level NoC.The quantitative analysis of two programs onmatrix multiplicative shows that the platform can be easily used for design spaceexploration.