Design And Implementation Of Configurable LDPC Decoder Based On FPGA

More and more practical communication systems use multi-rate QC-LDPC codes as theirchannel coding schemes to support the flexibility in code rate and code length. But thetraditional decoder structure can only support a single QC-LDPC code. To solve this problem,we present a Base-matrix based decoder architecture for multi-rate QC-LDPC codes, usingthe Modified Min-Sum Algorithm as the decoding algorithm, and finally a decoder isdesigned which can be easily configured to different code rate and length according todifferent service requirements and diverse interference conditions based on the language ofVerilog.First, we simulate the bit error rate performance of multiple QC-LDPC codes using MSKmodulation and MSK demodulation under the AWGN channel based on some existingcommunication system. We compared the complexity of hardware implementation anderror-correcting capability of several decoding algorithms of LDPC, and finally we confirmthe algorithm which is suitable for hardware implementation and the number of iterations.Based on the topic background, we employ the partial parallel architecture to implementthe decoder which can be configured to support different QC-LDPC codes. Meanwhile, tocooperate with the function unit, the messages storage topology is arranged the same as thebase-matrix and we call this decoder structure the base-matrix based structure. Based on thisarchitecture and decoding pipeline, we design the hardware structure of some primaryprocessing units and prove the correctness of all the modules through the timing simulation.Finally, we built a test platform based on ModelSim including LDPC encoder, LDPC decoder,MSK modulation and MSK demodulation to test the system performance. The test result isbasically the same as the theoretical coding performance, indicating that the architecture ofLDPC decoder is correct. In addition, in order to test the performance of configurable LDPCdecoder in acture hardware, we also implement a decoder using the same architecture whichcan support three QC-LDPC codes, and a hardware test system based on FPGA is designed totest its performance.At last, for the problem of the highly hardware implementation complexity of LDPCdecoder over GF(q), we give the deign scheme of general architecture and some elementarymodules, taking an example of LDPC over GF(4).