Research On TSV-aware Circuit Partitioning And Temperature-aware Floorplanning Of Three-Dimensional Chips

With the development of semiconductor technology and the growth ofapplication requirements， the bottleneck of development of traditionaltwo-dimensional chips (2D chips) is gradually becoming apparent. Especially underthe circumstances that the feature size is further scaling, the reliability of2D chipswill be sharply declined and the design complexity rapidly increased. Thethree-dimensional chips (also called Three-dimensional Integrated Circuits,3D-ICs) supply a novel solution to the IC industry.3D chips are constructed bysome dies stacked in the vertical direction through Through-Silicon-Vias(TSVs)vertical interconnect technology. For the emergence of3D Chips, the integration ofthe chip is greatly improved under the conditions of don’t need to change the chip’sfeature size. But there are also many puzzles unsolved to the3D chips. For example,the excess number of TSVs in3D chips occupies large chip area and increases themanufacture and design cost. The stacking of multiple dies makes the peaktemperature higher, thus degenerate the chips’ reliability and performance. Thethesis is a research right focusing on these two issues.First and foremost, a number of related terminologies and manufacturingprocesses of3D chips is introduced. And some crucial technologies are elaborated,some related work are analyzed and summarized.Second, for the excessive TSVs in3D Chips, the solution-Through silicon vianumber aware partitioning of3D ICs is proposed. The simulated annealingalgorithm is used to partition3D ICs, and the chip area and the number of TSVs areco-considered. The experimental results on the MCNC benchmarks have shown thatthe solution of the thesis can effectively improves the utilization of chip area, andreduce the number of TSVs.At last, for the high peak temperature in3D Chips, the solution-Temperature-aware Floorplanning of Three-Dimensional Chips is proposed. In thissolution, the concept of the "hot" block is proposed. During the process of3DChips’ floorplanning, we firstly fix the "hot" blocks to the bottom of the3D Chips,because the radiator near the bottom of the3D Chips is beneficial to thermaldissipation. Then, the opportune intralayer and interlayer heat constraints are usedto guide3D Chips’ floorplanning. The experimental results on the MCNC benchmarks have made sure that the proposed scheme can effectively reduces the3D Chips’ peak temperature.