| Through Silicon Via technology (TSV) for 3D packaging enables short and dense interconnects with increased speed and reduced noise. The goal of this project is a novel Via-first approach of bottom-up filling of through vias using copper DC plating. The Via-first approach fabricates TSVs before fabricating devices, with bottom up filling of through vias includes blind via formation, carrier wafer attachment, wafer thinning, and copper plating from the seed layer on the carrier wafer.;The process flow to achieve the fabrication of TSV in a novel way is described in this thesis. Blind vias with Bosch scallops were etched in a high resistance process wafer. The process wafer was attached to the carrier with an intermediate bonding layer. Thermoset, Revalpha thermal release tape, Wafer Bond HT250, and photo resist were used as bonding agents in this project. The process wafer was thinned by grinding and silicon blanket etching to expose vias from the backside. Via filling was achieved by bottom up filling from the seed layer on the carrier wafer and DC plating. The process wafer with copper filled through vias is debonded from the carrier wafer. The challenges encountered during each processing step and the corresponding changes to the process flow are clearly explained.;Irvine Sensors Inc. funded this project to achieve stacking modules with embedded integrated circuits and through silicon vias. Research was conducted at the High Density Electronics Center (HiDEC) at the University of Arkansas, Fayetteville. |
