Design Of Nods System For Seismic Data Acquisition On The Basis Of FPGA

Oil plays a very important role as the source of energy in supporting thedevelopment of economy. Strengthening exploration of oil resource holds greatstrategic significance. In recent years, along with the continuous development ofgeophysical exploration techniques at home and abroad, seismic exploration, as themost effective method in oil exploration, also gets further improvement. Besides, withthe development of electronic, communication and computer techniques, seismograph,the main device of seismic exploration, also gets the rise on its performance. At present,there are various kinds of seismograph devices. Through comparing their features,trends and timing at home and abroad, the paper puts forward the seismic data nodeacquisition system based on FPGA, combined with the modern signal acquisition andprocessing techniques.Currently, related products of the cable-less seismograph developed in Chinamostly use multi-CPU architectures such as ARM+FPGA architectures. The recoveryof seismic data, however, needs special recycling unit, such as Ethernet, to collect andrecycle, leading to long recovery time and low efficiency. Therefore, the paper,considering the characteristics of the cable-less seismic data node acquisition system athome and abroad, devises a scheme of embedded seismic data acquisition system basedon NiosⅡ soft core by adopting the designing idea and method SOPC (System On aProgrammable Chip), using Altera’s latest system integration development tool Qsys.The system can be used as a favorable solution to make the seismic data acquisitionsystem develop to the direction of low-power, digitization, high-integration andhigh-performance, combined with the characteristics of SOPC. For the recovery ofseismic data, the paper designs and realizes the seismic data storage unit on the basis ofFAT32file system format, which can copy the corresponding files as required to sort out the seismic data while recovering them. In this way, it can effectively simplify therecycling mechanism, and improve recovery efficiency.Focusing on the key techniques for the node system, such as power unit, dataacquisition unit, GPS clock synchronization unit and seismic data storage unit,considering the design and development procedure of Qsys system, the paper proposesthe research and design scheme of the following three phases.1. Design of Peripheral Hardware Circuits①Designing the power scheme, including the design of low ripple power and theanti-disturb design, to meet the requirements of long time measurement andfurthermore the low power consumption for the whole system;②On the basis of realizing specific functions, trying to take costs and circuitsdimensions into consideration, designing the peripheral configuration circuits and thestorage interface circuits needed by NiosⅡ soft core operation in FPGA;③Studying the features of seismic wave, designing seismic signal filter circuitsand AD transform circuits;④Choosing GPS clock module of high accuracy to design the correspondinginterface circuits;⑤According to the standards of SD card and CF interface, choosing SPI and trueIDE interface mode respectively to design SD card and CF interface circuits.2. Design of NiosⅡ Embedded HardwareCombined with the Qsys design flow, the Qsys system comes by adding the IPcore component capable of realizing all functions to the integration tools of the system.As for the situation where the Qsys platform fails to provide the IP core component(like the interface ADS1252), the paper programmed the user-defined IP corecomponent based on the Avalon bus structure in Verilog HDL. Though providing someIP core components which can be logically optimized to get overall promotion of theirfunctions (e.g. the PIO core as used in the1pps of GPS time service module and the SPIcore used in the SPI mode of SD card) by aiming at the platform, the paper adopts thebottom-up design for the top level module, employing the corresponding controlmodule in Verilog HDL, and verifying by simulating in Modelsim.3. Design of NiosⅡ Embedded SoftwareIn the integrated development environment of Nios Ⅱ11.0Software Build Toolsfor Eclipse, the paper employs C Language to conduct program design. Combined withthe mapping offset address of the register of every interface, the register can be visited directly in the way of structure in order to realize the dynamic control of each interface.Furthermore, seismic data acquisition and the rapid response of GPS timing controlsignal can be achieved by interruption. Meanwhile, the function of the entire systemcan be finally realized by transplanting the efficient file system model FatFS andadopting the timing storage of seismic data in FAT32format.With the completion of the whole system design, this paper comes to the followingcomprehension and results:1. System integration is promoted effectively and the overall power consumptionis reduced for SOPC is employed to realize the functions of seismic data acquisitionnode system;2. The methods of seismic data recovery are improved, and the recovery efficiencyis effectively promoted when using the FAT32file format with strong compatibility tostore seismic acquisition data of nodes;3. Through the user-defined design of ADS1252IP core, the sampling timingcontrolled by the internal state machine can be realized. The software only needs toread and write the related control register of interruption to complete the whole ADacquisition process, which can effectively improve the execution efficiency of theprocessor program.4. The thesis designs seismic signal pre-accessing circuits where the amplitudefrequency curve of the filter circuit is flat and the resolution of A/D converting circuitAD at its sampling frequency interval can completely satisfy the requirements of theseismic acquisition.