Research On LDPC Encoding For Power Line Communication And FPGA Implementation

Power Line Communication(PLC)is one of the most important communication methods in the construction of modern smart grid.It is widely used in intelligent home,energy control and meter reading.Low Density Parity Check Code(LPDC)is a research hotspot in recent years.LDPC codes can be applied to almost all channels and have excellent error correction performance,close to Shannon's capacity limit and anti-burst error.In addition,the iterative decoding algorithm used in LDPC codes can achieve parallel operation and increase throughput,which can improve the transmission efficiency of the system and facilitate the implementation of the hardware.Aiming at the multipath delay effect and colored background noise of power line channel,this paper studies the decoding algorithm of LDPC code in power line communication channel.LDPC code can overcomes the impulse noise of power line channel by its excellent error detection and correction performance,combined with OFDM modulation technology.It also greatly overcome the power line channel multipath fading,making power line communication more reliable and effective.Firstly this paper studies the performance characteristics of LDPC codes by using MATLAB software.Secondly,by comprehending the G3-PLC protocol of power line standard,an improved G3-PLC physical layer code is proposed by using the coding and decoding module of LDPC code,which provides a reference for the system design of LDPC based on the G3-PLC specification.Finally,I use Verilog programming to realize LDPC coding and decoding and raise the overall framework and main functional modules of the decoder by using FPGA as the hardware platform.Through the QUARTUS II software,the main function modules of LDPC code decoder are simulated.