Borehole Radar Receiver Front-end Design

The borehole radar, as its name suggests, is a ground penetrating radar (GPR) which works in the borehole underground. It is widely used in environmental protection, resources survey, archaeological excavation and many other fields. Research into the borehole radar has a great significance for our country to make up the shortage of the commercial borehole radar’s development and production. As an important part of the borehole radar, the receiver exercises a crucial influence on radar’s overall performance. Therefore, how to design a high-performance, low-cost and easily-produced receiver is becoming an important dimension of the borehole radar analysis nowadays.The main research in this dissertation is the design of the front-end of the borehole radar receiver, which includes the limiter, the T/R switch, the variable gain amplifier (VGA), the sample-hold circuit and the relevant control circuit. According to the system requirements, the front-end circuit is designed, simulated, processed and tested. Then, based on the system problems found in practical applications, improvement and perfection of the relevant parts have been made to meet the practical needs.According to the working environment of this borehole radar, the system has the following requirements for the receiver:Firstly, the working frequency range should be60MHz-180MHz. Secondly, it must be capable of receiving pulse signals with a6～10ns pulse width. And for each pulse signal,8～10points are sampled. Thirdly, the receiver is required to have a0-60dB variable gain with the step of lOdB. Fourthly, the system noise figure should be less than2.5dB when the gain is60dB. Besides, the receiver should also involve an auxiliary circuit to ensure that the system can work safely and reliably. In this dissertation, the main discussion is centered on the design of the receiver’s front-end to implement all the above requirements.For the purpose of eliminating the effect of the direct wave between the transmitting and receiving antennas, a limiter together with a high speed switch is added in the front of the receiver. The limiter is capable of restraining the intensive direct wave signal by the diode to prevent it causing damage to the follow-up switch and amplifier. After that, the direct wave signal which has been already cut off the peak value will be removed by the switch for the purpose of protecting the circuit.The variable gain device which is composed of different amplifiers, including30dB,20dB,10dB amplifiers, is connected to the circuit. By controlling the switch the gain ranges from OdB to60dB. Besides, the on and off of the amplifier’s power should be taken into account to prevent the system from interference or even being unstable.The system adopts the equivalent sampling method with a repetition rate of10kHz. And the sample-hold circuit contains two stages of synchronous sampling. The first stage includes a holding capacitance and a selector switch with very high speed in ps level. The hold time of the signal after sampling should be hundreds of nanoseconds. In the second stage, we use the AD783sample-hold chip whose sampling time is200ns and its hold time can meet the requirements of the back-end signal processing with a repetition rate of10kHz.The receiver’s front-end circuit designed in this dissertation has already been applied into the actual radar system. Through working tests in a simulation hole, the receiver is proved to be capable of meeting the system’s electrical targets and functional requirements. Thus it has attained the goal of the design.