The Design Of Cmos Charge Pump Phase-locked Loop Circuit

Phase locked loop (PLL), which can provide an accurate high-speed clock for synchronous digital circuits and can be applied to communication modulations, is a kind of feedback system. As an essential module in modern electronics, PLLs are widely applied in CPUs of personal computer,3G cellular phones, bluetooth devices etc. Since the working frequencies of portable electronic products such as cellular phones and tablet computers are rising rapidly, quartz oscillators cannot provide high-speed clocks for these systems at the frequency range of GHz. This indicates that PLLs are requisite in these application fields.By using Tanner EDA software, this subject proposed a kind of charge pump PLL clock generator which is composed of PFD, charge pump, VCO and frequency divider. All the work was accomplished based on TSMC0.25μm CMOS technology. The PFD composed of digital gates can implement phase and frequency detection; the charge pump is of stand-by current architecture which can speed up the lock velocity, its speed is1.2V/μs and0.9V/μs for raising voltage and descending voltage respectively; VCO whose frequency range is200MHz—800MHz is of four-stage ring architecture, the maximum frequency gain is1082MHz/V; the frequency divider is of three-stage TSPC D flip-flop asynchronous architecture which can work well under high-speed conditions. After simulating all the modules, the PLL system is well studied, the output frequency range is400MHz—600MHz, the locked time is less than5μs due to employ the stand-by current source architecture. Finally, the layout was accomplished, the total area is3330μm2.