With the development of science and technology, digital television is replacing analogue televison, which greatly improves the quality of people’s lives. In order to acquire more flexible and comfortable viewing experience, it is of great significance to research receiving more than one format television on one chip.This paper mainly studies the key technologies of the multi-mode digital TV (DTMB/CMMB) demodulator, which includes DTMB/CMMB demodulation, DTMB channel estimation and DTMB decoding. The work involved in this paper is as follows:Firstly, this paper researches on the fundamentals of the Fast Fourier Transform (FFT) algorithm, which is the common technology for demodulation of DTMB and CMMB. In terms of the characteristics of multi-mode digital television receiver, this paper studies and proposes a3780/4096points (DTMB/CMMB) FFT processor algorithm suitable to our system. Based on the algorithm, the implementation method of FFT processor is proposed, and the fixed point width of each block is decided by simulation. Durring the implementation, the3780point FFT processor uses the in-place method. This method replaces a4096X42bit RAM with a3780X12bit ROM compared with traditional methods, which greatly decreases the area and power consumption. The SNR, resource overhead and operation speed are acquired by simulation and synthesis of the FFT processor. Secondly, the algorithm of channel estimation in DTMB system is reseached and a Fast Walsh Transform (FWT) processor is proposed according to the algorithm. We got the performance of the FWT processor through simulation and synthesis. In the end, algorithms of BCH decoder and LDPC decoder are discussed here and the structure of LDPC decoder is presented.At last, these blocks are implemented on the Stratix IV platform. The results shows that all these proposed blocks can meet the requirments and both of DTMB and CMMB televisions can be demodulated by this system. |