Algorithm Design Of 3780-point FFT Processor And FPGA Implementation In DTMB System

Digital Television Terrestrial Broadcasting is one of the hot technology in the wireless field recently, it breeds a opportunity to create a new market for mobile TV, and has bright future. The Chinese digital terrestrial television broadcasting standard with independent intellectual property, named "Frame structure, channel coding and modulation for digital television terrestrial broadcasting system" was published on August 1^st in 2007, which stands for DTMB in English. The issue and actualization of Chinese DTTB standard established the foundation for the development of Chinese terrestrial DTV, and started up Chinese DTV market.DTMB standard adopts Time-domain Synchronous Orthogonal Frequency Division Multiplexing (TDS-OFDM) to be the key technology of transmission. In order to achieve the TDS-OFDM technology, the 3780-point fast Fourier transform (FFT) processor is one of the important and indispensable modules. Based on the analysis of the current situation and the development of digital TV and Orthogonal Frequency Division Multiplexing (OFDM) technology, the following aspects are deeply analyzed and researched.Firstly, this paper studies the current main algorithm of FFT, including radix-2 algorithm, the Cooley-Tukey FFT algorithm, Good-Thomas prime factor algorithm (PFA), and Winograd Fourier algorithm (WFTA), and so on, then concludes the important algorithm. Every FFT algorithm has its strengths and weaknesses, how to choose is needed to according the actual system.Secondly, this paper discusses a variety of 3780-point FFT designs particularly, and does complex analysis about how to decompose the 3780-point FFT algorithm. In accordance with the characteristics of the DTMB system, through a number of exploration and analysis, a 3780-point FFT algorithm design that is suitable for the DTMB system is represented. And then simulation platform is built for C fixed-point simulation and verification. This algorithm uses PFA, the Cooley-Tukey FFT algorithm, WFTA synthetically, decomposes 3780-point down to every level, and thus greatly reduces the complexity of the algorithm.Thirdly, based on the analysis of FPGA design and development process, this paper uses the pipeline structure for the hardware design of the 3780-point FFT processor, which greatly increases the throughput of the system, and eventually completes the consistency verification process and integration process of the circuit.According to the simulation of hardware and software, it shows the FFT processor meets the signal to noise ratio requirement of the TDS-OFDM system, and greatly reduces resources required for the logic applies, it's applicable to the requirements of national standard modulation and demodulation system.