Design And Implementation Of Time Control Circuit Of Read-Out Integrated Circuit For Uncooled Infared Focal Plane Array

Infrared focal plane array (IRFPA) is the core chip of infrared imaging system. The chip includes detector and readout circuit (ROIC). ROIC mainly processed the detector signal and exported the signal to the imaging element. This paper first introduce the principle of detector, then study the ROIC. ROIC can be divide into analog circuit and digital circuit, and digital circuit mainly control the timing of switch of detecor’s row and column, so it can be called time control circuit. The meaning of this paper is this design belonging to commercial IRFPA. Due to start lately, there is just military but no commercial production in my country.This design is to320X240IRFPA, the scale of time control circuit is not large and the function is not complex, whether the semi-custom method or full-custom method is suitable has not conclusive. This design first takes full-custom method. Confirming the overall circuit structure, we can sure the function of analog circuit and digital circuit. Then we make the timing graph and attempt some special circuit module to reduce the power and area. After that, we make the schematic, simulation, layout and post-simulation. We also take semi-custom method to design this circuit. Confirming the function and timing, we make the Verilog code and simulate it. Then we take the EDA software to do logic synthesis, place and route, timing analysis, etc. The hard point of this design is studying the work mode of the EDA software and learning the operating procedure of it. The industry always took the method of automatic design with EDA to design digital integrated circuit, and all of the existing ROIC design took this method. In addition, this paper taped out the two designs, and we created PCB to test the chip. The results of the test show the power consumption of the full-custom design much lower than the semi-custom. In fact, we can get the layout area of full-custom design also smaller than semi-custom.This design is completed by CSMC0.5μm DPTM single-well process and many EDA tools of Cadence and Synopsys, Inc. Due to the time consumption of studying the EDA tools in semi-custom design is more than the full-custom design, this paper will first discuss the semi-custom design.