Signal Intergrity Analysis In High-Speed Signal Circuit

The problem of signal integrity is a key issue in the design of high-speed circuits, and ithas a wide range of applications in many fields, such as intelligent control, high-speed capture,radio frequency circuits and so on. It aims at analyzing the signal interference levels affectedby some factors, such as the reflection noise, crosstalk noise, time series, power supply noise,electromagnetic radiation and so on, and to provide important parameters for the systemcircuit design and PCB layout, and eventually to improve the signal transmission quality. Withrapid development of high-speed circuits, the signal integrity issues become increasinglycritical. As the signal integrity issues are affected by various factors, the traditional signalintegrity handling methods, such as simple capacitor filter, the via array processing methods,can not meet the requirements of circuit design. Especially under the condition of highfrequencies, the signal is seriously interferenced by many factors and difficult to control,whichis very easy to be distorted.This article focuses on the key technologies of the signal integrity problems underhigh-speed condition. The main work includes:1. To solve the problems of serious reflection noise of the difference clock signal underthe high speed circuit, an improved differential signal termination design isproposedbyintroducing the single ended impedance matching to the drive, in order to suppressthe reflection noise. At the same time, a further analysis on the influence of the improvementdifference termination design by the signal frequency and the transmission distance are made.We make a simulation analysis on high-speed board. The simulation results show that whenthe signal is less than 500 MHz, comparing to the common alternating coupling terminationdesign, the improvement method receives the signal overshoot reduced by 10.9%, andimproves the difference clock signal quality in the high-speed data acquisition system, andverifies the effectiveness of the design.2. To solve the crosstalk noise problems in the high-speed circuit, firstly we analyze thecrosstalk noise influences of several common parameters, such as line spacing, line parallellength, and medium thickness. According to the actual situation, designs should meet theconstraint conditions of those common parameters. And we make simulation analysis after thewiring to check the conditions. Secondly we study the influence of the different terminationdesign and via spacing of protection zone about crosstalk inhibitory effect. The simulationresults show that reasonable termination design and via spacing of protection zone couldsuppresse resonant. It provides important data for the actual circuit design. 3. To solve the timing problems in high-speed circuit, it establishes the simulationplatform in Hyperlynx through effective device model (IBIS model). It modifies the set-uptime and the hold time provided by device data handbook, so the output delay of the clocksignal can be determined. Moreover, based on the timing requirements of DSP and SDRAM,designs should meet the wiring constraint conditions of the PCB layout. Hence, layoutengineers can use our proposed rulers to design their board.4. To solve the power integrity problems of the high-speed circuit, the article proposes amethod of inhibiting parallel resonant of PDN through increasing decoupling branch loss. Itintroduces a series resistance into the decoupling branch to make PDN loss increase, whichsuppresses PDN parallel resonant. The theoretical model is provided and supported bysimulation experiment on Hyperlynx PI software. The results show that, the quality factor ofPDN at parallel resonant will be inhibited from 282 to 13 through introducing a 0.45 resistance into decoupling branch. This paper also analyzes the effects of the introducingresistance to decoupling. When the introducing resistance is less than 0.45 , it cancompensate for the influence of decoupling through doubling the number of decouplingcapacitors.