Research And Optimization On Low Power Floating Point Multiply ADD Fused Unit

Floating-Point Fused Multiply-Add(FMA)Unit is one of the core computing components in high-performance microprocessor, its speed and power consumption have great effect on the performance of entire microprocessor. Along with the increasing requirement of low power, it becomes significative and valuable in practice to achieve a FMA with high performance and low power.Multiplier has large area, long latency and consumes considerable power. It becomes attractive how to optimize the design of multipliers from architecture, gate level, and circuit level with more attention on the three aspects of area, latency and power. The following work has been finished in this thesis:(1)The encoding is the basis of the rapid multiplication. Considering the impact of the coding results on the probability of the multiplication circuit switching, c a low-power Booth encoding method was selected from a variety of encoding methods(2)During the multiply-add operation, the process of Partial product reduction occupied the most resources, this thesis had a analysis of 3:2CSA compressor and 4:2 binary compressor, and proposed a new 4:2 compressor with improvement on area and power consumption.(3)The leading zero prediction algorithm design is an important part of the design of high-performance floating-point multiply-add units. However, the prediction might be in error by one bit. This thesis proposed a new algorithm to correct LZA prediction error. And this algorithm has the obvious advantage of the power and area with the comparing with the other algorithms(4)A new structure was introduced to achieve low-power multiplier design. The multiplication circuit could be divided into smaller multiplier groups, reducing the switching activity of the circuit, thus achieving the goal of reducing power consumption. By using clock gating techniques and preprocessing operation on the input data with logic circuit, the groups that producing 0 could be disabled, so that the power used for circuit switching could be saved. For testing purposes, an 8 bit multiplier was designed, using Candence software, 0.18 um technology. All possible input combinations had the same probability. Hspice simulation results showed that this structure saved 13.36% power consumption.