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Ic Manufacturing Lithography Process On Silicon Wafer Edge Wave Problems In The Research

Posted on:2013-02-05Degree:MasterType:Thesis
Country:ChinaCandidate:A K MaoFull Text:PDF
GTID:2248330371465467Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
Lithography process is one of the most important semiconductor manufacturing process steps, it is used to copy mask plate pattern on the silicon wafer for next Lithography step. Lithography process’s basic requirement is the high resolution and low defect density. With the wafer size become more and more big, the CD is more and smaller, earlier process is not very concerned with the edge of the silicon wafer, but now it became more and more serious. For the increase of the silicon wafer size, the wafer’s perimeter increased. The truth of the CD became smaller, leading to effective chip number around silicon wafer edge also have increased by multiply. So lithography process fluctuation problem in the edge of the silicon wafer becomes more and more important, it has a great significance to improve the yield and production efficiency.From the experiment, in 0.6 micron HVMOS process, through electron microscopic observation, in the partial shot of wafer edge, the pattern like column is defocus. From the research, there are three effective ways to solve the wafer edge defocus issue, 1)through focus and flatness to detect the width effectively; 2)adjust the focus plane to the positive direction; 3) manual control AF detection point position.In 12 inch 90/45 nm process, lithographic equipment has a greatly improved, while the increase of RET, it seems that all attention on how to make the CD smaller, but if the improvement of resolution, DOF will exponentially decreases, and the sensitivity of the wafer edge will becomes higher, it will lead to edge process deviation more fluctuations. For the 12 inch wafer, we can find the defect source exists in wafer edge; its defocus problem is very serious. EBR plus WEE mode of silicon wafer can clean wafer edge’s photo resist residue, in it, WEE cleaning setting wide is smaller than EBR’s, which will achieve the precision cleaning width and removed wafer edge residue from EBR more clearly. From the experiment results, when the EBR&BACKRINSE time increased to 15s, and the spin speed increased to 1500r/m there will be a relatively clean bevel. In principle, it is to increase the volume of liquid medicine and reaction time to edge to let more solvent to remove wafer bevel photo resist residue, while increasing the rotational speed can make the back-rinse more solution turned up to the wafer edge to clean wafer bevel, all these can eliminate the wafer edge process fluctuation from bevel residue.In short, whether it is 8 inch or 12 inch or 18 inch in the future, wafer edge problem will be placed in a very important position. Wafer edge problems caused by many factors, substrate thickness difference, and wafer bevel pollution problems, these external factors are uncertain, but a photolithographic process itself is relatively complex and flexible methods and tools. In the factory, output and cost are the two most important elements, when adding a process step, the cost will increase and it will impact the wafer throughput. Therefore in common situations, FAB would rather optimize the photo process to cover the substrate or process problems than adjust film thickness or change etch rate. Therefore the lithography will be higher requirements, but it can also play the advanced lithography tools and techniques to the extreme.
Keywords/Search Tags:Photo lithography, wafer edge, process, focus, resolution
PDF Full Text Request
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