Astronomical Image Difference Algorithm Design And SOC Special Hardware Realization

With the rapid development of processor technology, microprocessor has a large range of applications to a certain extent, and configured processor to the specific application processor can be properly configured, thereby we can get different operational module hardware circuit. Programming through its management, we can achieve the ultimate function of the realization of it. With a configurable processor to complete the data intensive computing tasks, configured processor has stronger computing capacity than the general purpose microprocessor, has more flexibility compared to ASIC ( Application Specific Integrated Circuit ) structure, can accelerate the development cycle, at the same time in the power consumption is lower than the general digital signal processor. This paper designs a astronomical image difference algorithm for reconfigurable processor template - T * Core, the processor is based on the transport triggered architecture (TTA, Transport-Triggered Architecture ) design. After selecting application, depending on the configuration of relevant parameters can be generated for a specific domain of T * Core processor hardware circuit.In this paper the difference algorithm for astronomical image with a detailed analysis of induction, reduced clarity of function, kernel function and related solution methods under different environmental circumstances sky background analysis and processing. These analysis, as T * Core functional unit of the processor is designed to provide the basis of algorithm, T * Core structure contains a whole architecture design, internal core unit, instruction format, lines, network access, memory and the final system addressing and so on. Which algorithm based function unit is affecting the entire processor key components, and not only the real-time data processing plays a key role, effective and reasonable for its optimization, but also can improve the overall speed.In hardware verification, this paper uses XILINX FPGA’s XUPV5-LX110T series MACROBLAZE as the main processor, T * Core as a co-processor, to build an embedded SOC (System on Chip) development system. Achieved through the SOC, the system frequency eventually went to more than 100M. T * Core processor hardware architecture design has passed the pre-simulation, verification and final board-level system debugging. In order to further improve the speed, we use multi-core heterogeneous T * Core processor parallel processing program, which can fully play T * Core processor data-intensive computing features. Achieved by the end of the SOC, T * Core processors has the correct function on the basis of calculation and increases the speed effectively compared to common PC software. Power consumption has been greatly reduced, dual-core power consumption is only 2.3% compared to software. Achieved by this architecture, proving once again that T * Core processors can achieve real-time and low power requirements.