Research On Power Line Communication Synchronization And Channel Estimation Algorithm And FPGA Implementation

With the rapid development of Smart Grid and smart house, the demand for powerline carrier communication chip increase sharply. The study on PLC technology cangenerate enormous economic benefits while can also promote the development of PLCtechnology in China at the same time. Civil PLC chips mainly adopt single carrier andspread spectrum modulation technology,only suppose to the function of reading meter.And it cann’t meet the requirements of the smart grid and smart home. Based on OFDM,PLC technology with high bandwidth efficiency, weak anti-channel capability, suitablefor high-speed transmission, and anti-inter-symbol interference features, which has awide application future, is the core technology of the third generation PLC chip.This paper introduces G3-PLC physical layer protocol and research on the basicprinciples of the mapping and demapping, the modulation and demodulation, the cyclicthe prefix,the windowing and the farming on OFDM baseband system on G3technicalstandards. OFDM baseband system is simulated using MATLAB which was also appiedto verify the hardware simulated results.Power line carrier communication synchronization algorithm are proposed basedon the OFDM. According to the impact of synchronization offset on OFDM systems,combined with the actual situation with the system, the classical frame synchronizationalgorithm is improved and is proposed to the threshold keep method to prevent falsealarm phenomenon. The principle of the frequency synchronization was analyzed andthe range of the frequency offset estimation was acquired. Also the traditional symboltiming algorithm is improved. The simulation shows that the improved algorithm isadaptive to threshold and the performance of conquering the interference of side lobe isbetter. And it is easier to design in hardware.Power line carrier communication channel estimation are proposed based on theOFDM. The characteristics of the low-voltage power line channel is analyzed and theLow voltage power channel model is set up.the LS (Least-square), MMSE (MinimumMean Squared Eorror) and SVD (Singular Value Decomposition) frequency channelestimation algorithm are further researched. The performance and complexity of thesethree algorithms are compared with each other.The realization method of each module’s synchronization and channel estimationusing FPGA is introduced. The hardware block diagram is given in each module and also does the detailed steps in the process, as well as in the Modelsim simulationgraphics. Finally, the program, which is get through from the function simulation, isdownload to the FPGA for timing simulation. The comparison between the results ofFPGA implementation and algorithm simulation shows that the new optimizingalgorithm and FPGA implementation are reasonable.