Design And Implementation Of The OFDM Synchronization And Equalization Method Based On FPGA

Since the invention of orthogonal frequency division multiplexing (OFDM), has been widely applied in various fields of communication, because of its strong anti-multipath effect ability and high frequency efficiency. However, the performance of OFDM technology will reduced by its low tolerance of frequency offset. It is also a serious situation of the decline of wireless channel. Due to the randomness of the arrival data in burst communication, it is a problem to enable the location of frame data accurate. The consumption of resources should be reduced in the process of complex algorithm in the reality. Therefore, It is significant to research the technology for OFDM synchronization, equalization and hardware implementation.Firstly,the importance of synchronous technology in OFDM system is analyzed in theory in this paper. A system data frame format benefit for hardware implementation with flexibility in design has been summarized. An algorithm for calculating the system parameter based on the above frame format is presented, and a related example is given. The algorithm of synchronization, channel estimation and equalization that suitable for OFDM system and easy for implementation are analyzed in the next.The OFDM communication demonstration platform fully-digital implementation scheme is given in this paper, and the system is built by using FPGA, the main part of the receiver system is implemented. The implementation scheme including the frame detection module,the frequency offset estimation and compensation module, the symbol synchronization module, the channel estimation and equalization module and residual frequency offset correction module are introduced. The main function of all above modules and the specific method to implementation of its secondary module, triple module are explained in details. A lot of simplified methods are used in the process, such as the consumption of resource in multiplication operation is reduced at the sacrifice of time by using the speed and area interchangeable principle. By using the variable threshold value in the de-mapping module,all division operations are all avoided through the optimized algorithm, Which enables the system structure more simple and reduces the system complexity.Using the Xilinx company’s XC5VSX95T of Virtex-5 series as the core processor, the ISE 14.3 as the compile software integrated development environment, the hardware description language Verilog HDL as the main programming language, the FPGA design of fully-digital communication system is built. The system simulation and debugging the programming by Modelsim 10.1c are conducted after above mentioned being set up. Finally the correctness of system is determined compared with numerical simulation result and ChipScope Pro, and code for simulation is executed successfully on the development board.Every module complexity is reduced by the simplified method in the paper compared with similar literatures.