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The Research Of Multiple Point Control Protocal Designed With FPGA And Forward Error Correction Baesd On EPON

Posted on:2013-02-25Degree:MasterType:Thesis
Country:ChinaCandidate:F R LiuFull Text:PDF
GTID:2248330362469974Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
In recent years, along with the demand of service with image, data and voice have beenincreasing dramatically, people require the bandwidth of access network to become higher andhigher.However, the bandwidth of existing access network which is presented by xDSL can’tmeet the demand of people. Optical access network has many advantages, such as transparentservice, strong carrying capacity of bandwith, adapt to the growing bandwith and new service,consequently, it become the inevitable trend of access network. Because of the advantages ofEthernet Passive Optical Network and lowcost, it becomes one of the predominant techniquesof next generation broadband access.In this paper, multiple point control protocol designed with FPGA and forward errorcorrection in EPON has been investigated. Firstly, the structure of EPON, working principle,key technique, and the operating principle and frame structure of multiple point controlprotocol have been analysed. Secondly, the design proposal of MPCP function in OLT andONU have been elaborated, and it is implemented with Verilog HDL.At the same time, thecorresponding function simulation results have been given.Finally, the block diagram of FECencoder and decoder have been designed, and the design proposal of RS(255,239) encoderand decoder which are designed with FPGA have been emphasizesed,and the functionsimulation and hardware test of the design proposal implemented with FPGA of RS(255,239)encoder and decoder have been done. The main research of this paper can be divided into twoparts. On the one hand, the design proposal of multiple point control protocol in EPONimplemented with FPGA is put forward, and the function simulation of which has been donein the ModelSim SE6.5. On the other hand, the RS(255,239) encoder and decoder realized byFPGA and its hardware test have been done, the test results validate the fesibility and validityof the design proposal of the encoder and decoder.
Keywords/Search Tags:Ethernet passive optical network, multiple point control protocal, forward errorcorrection, FPGA
PDF Full Text Request
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