Ethernet Passive Optical Network (epon) Equipment, Hardware Design And Debugging

With the rapid development of Internet services, higher and higher requirements of network bandwidth are needed. Since the backbone has already the adequate ability to sustain the broadband, access network bandwidth becomes the bottleneck of the whole network. As a solution for access network, EPON (Ethernet Passive Optical Network) has mature technology and broad application of Ethernet. It has a Point-to-Multipoint Architecture and provides Multi-Service basing on Ethernet. It combines the advantage of PON technology and Ethernet technology. With its features of high bandwidth, low cost and being used and updated easily. EPON is the best solution for access network. With EPON international standard—IEEE802.3ah was released in 2004, the industry alliance of EPON has appealed many manufactures to participate actively. Now in North America and Japanese FTTH has been developed in a large scale, and in our country the experiment of FTTH has been started in some places. So far, some manufactures have supplied hardware solutions and software on networking management of EPON. But most of them are in commercial experimental phase.In this thesis, the main work is focusing on the hardware design and debugging of EPON. First, establishing the overall plan of the hardware system and ascertaining the type of the core chips based on the function what will be needed to perform. Considering the access function, Passave EPON chip group is selected as the central office interface and user network interface MAC chips. Considering the network management function, PowerPC405EP is selected as the main processor chip. Second, two PCB boards design are completed. One is for the Ethernet network interface between the up direction of OLT and the backbone network with the bandwidth of 1Gbit and OLT's optical interface; the other is for the user network interface with the rate 10/100M of ONU and its optical interface to OLT. Some relevant interfaces are also processed specially. With regard to the debugging of OLT and ONU, the PASSJTAG package and the parameter configuring of EEPROM is accomplished in order to realize the initialization of the main chip, the configuring and the choice of the function pattern. These chips are accord with the standard of 802.3ah,and provide different interface. The system we designed can resolve the requirement of the access network.The interfaces using for network device management, boot configuration and debugging are also indispensable. In order to make the network system operate at a high speed and efficiently, the embedded Linux operation system is used for recording and accessing kinds of parameters. Except for that the operation system also can be used for completion the transition of different protocols. The hardware device with the main chip PowerPC405EP which is called HOST CPU is used as the platform of network management agent. Through HOST CPU, administrators can monitor the status of link, collect the parameters and deal with the malfunctions in a real time and long-range. The hardware interface of HOST CPU is using Local Bus to connect with the MAC chip of OLT. At the same time, in order to update conveniently, some expendable interfaces also processed accordingly. The debugging work of HOST CPU is complicated. Besides completing the debugging of Local Bus and its relevant signals, the driver between the OLT MAC and CPU is indispensable. The combination of hardware and software debugging is used, and an advanced and efficiently access mechanism between HOST CPU and PON is established. Then the operation status of the device can be monitored and managed real time.