Design Of Front-End Readout Circuit For Cryogenic Infrared Focal Plane Array

Infrared focal plane array detectors (IRFPA) are important conponts to abtain infrared information, thus they are widely used in military and many other fields. Readout integrated circuit(ROIC)is the core part of IRFPA, the performace of ROIC will greatly decide the performace of the IRFPA.Based on Chartered 0.35μm 2P4M CMOS process, a front end readout circuit for a 512 512 ocal plane array detectors is proposed in this paper, the size of each cell in in this design is 30μm 30μm. The circuit mainly consists of the front end readout cell (CTIA) and the signal processing circuit (column charge transferring amplifier, column buffer, output buffer). The timing control of the whole circuit and principle of each part are fully analyzed in this paper. A low power comsuption and small size readout cell is carefully designed according to the requairements of the IRFPA system; a charge transferring amplifier circuit is designed to avoid using drive circuit in cell based on the parasitical parameter analysis; a rail to rail class AB amplifer with transfer rate of 12MHz/25pF is used as the output buffer; meanwhile, low power comsuption design is introduced in this circuit; based on the design, the layout of the whole circuit was completed, and the taped-out chip was carefully tested.The tested result shows the circuit has a good response to the infrared signals, the integrated time and integrated capictance can be adjusted by signals given outside of the chip. Output signal rate could reach almost 5MHz, low power comsuption design works well in the circuit. But there is vibration at the output stage, the possible reasons are discussed in this paper.