Study On Bionic Roic For Irfpa

Infrared focal plane array (IRFPA) is the core component of infrared technology, and has been used widely in many fields of the military, science, astronomy, and civil use. With the expanding of array size and application, modern infrared focal plane large-scale array still is expected to be able to detect and identify interesting objects under high output frame rate, requiring successive interface and processing circuit with higher performances. More signal processing functions are desired to be integrated on-chip to improve the integration level to reduce requirements of the successive interface and processing circuit, enhance the overall performance of IR systems, and reduce the size, power consumption and cost etc. This project is supported by NSFC(No. 60702007).Imitating the image acquisition and processing of vertebrate retina, and integrating bionic retina signal processing circuit on the Focal Plane Array (FPA), bionic circuit of photoreceptor, horizontal cells and bipolar cells are implemented for extracting the image edge information. Retinomorphic circuit consists of adaptive photoreceptor, 2-D resistive network with simple structure, and Operational Amplifier (Op-Amp) processing circuit. Current-mode background suppression circuit eliminates background current. Logarithmical signal conversion from current to voltage is implemented by the adaptive photoreceptor. The output voltage of the adaptive photoreceptor is spatially smoothed by 2-D resistive network. The output voltages of adaptive photoreceptor and resistive network are added or subtracted by Op-Amp processing circuit to achieve on-chip edge detection or contour enhancement. Different effects of edge detection or contour enhancement could be realized through adjusting the bias voltage of resistive network.This thesis studied on the adaptive photoreceptors proposed by Delbruck and made some improvement on it, so that the output voltage of the photoreceptor is adjustable. Mead's classic filtering network is simplified, and a resistive network with simple structure, small size and low power consumption is proposed. Improved resistive network, achieving image spatial smoothing filtering, is more conducive to integrate on-chip. And the filtering effect is adjustable.Circuit simulation and layout design were implemented using Chartered 0.35um 2P4M CMOS process. Simulations of image edge detection by 6×6 array and image contour enhancement by 16×16 array are carried out respectively. Layout of edge detection 10×10 array is designed and fabricated.