Real-time Simulation Of Low-Voltage Power Line Communication Channels Based On FPGA

Low voltage power line is a time-varying system of complex network structure, whose hostile channel properties such as very low impedance, instability channel frequency, strong noise pollution, attenuation and time-variance must be considered. The complexity and variability of low-voltage power line network are the key factors for the reliability and stability of Power Line Communication (PLC). It is necessary to have a full understanding of PLC channel to achieve a high-speed and reliable communication system. Therefore, channel modeling has great significance to realize the PLC and other related technology research.A simplified PLC channel model based on FPGA is presented by analyzing the characteristics of its channel and understanding scholars'theory analysis and simulation validation based on the channel modeling. The frequency range of the proposed model is 1 ~3MHz. Using top-down design method, a real-time simulation system of this model is realized by FPGA. The system is composed of 4 parts, input pretreatment, channel simulation, noise and output pretreatment. This paper introduces the process of realizing the four modules by FPGA. MATLAB is used to design the coefficient of FIR filters and the correctness of each module is proved through the simulation of a third tools—Modelsim.In this paper, the resource utilization of the FPGA-based channel is analyzed, which shows that the channel model is real-time and reliable and is able to reflect the essential characteristics of the actual low-voltage PLC channel. The FPGA has the advantage of flexible programming, short development cycle, low cost and real-time online testing. To meet the requirements of real-time and low cost, the FPGA is taken for real-time PLC hardware simulator, which is helpful for improving on-site debugging of PLC equipments. Finally, four modules are synthesized in the project of FPGA to make a complete system. The FPGA chip model is chosen to build hardware test platform and analyze the utilization of the resources in FPGA when the system is running. The results show that the system is stable.