Research On Modeling And FPGA Resource Optimization Methods Of Power Electronics Hardware-in-the-Loop Simulation System

With the increasing switching frequency of the power electronic system,the traditional simulator based on CPU processor or digital signal processor cannot meet the precision requirement of real-time simulation of high frequency and multi-switch power electronic system.In contrast,the FPGA(Field Programmable Gate Array),with its excellent parallel data processing capability,high clock frequency,excellent reconfigurability,and scalability,has quickly become the preferred option for real-time simulation of power electronic systems.Power electronics system modeling is an important factor affecting the performance of hardware-in-the-loop(HIL)real-time simulation system.Because the traditional modeling method is difficult to effectively realize the real-time simulation of high frequency and multi-switch power electronic circuits,it is necessary to propose modeling improvement method.At the same time,the balance between simulation accuracy and FPGA resource consumption is also very important,in which the variable bit-length and time step have a great impact on model accuracy and FPGA resource consumption,but the detailed quantitative analysis is lacking at present.Therefore,it is an important issue in the field of real-time simulation of multi-switch power electronic systems to improve the existing modeling methods and select quantitatively the minimum bit-length and the optimal time step that meet the modeling accuracy requirements to optimize FPGA resources.In this paper,ADC(Associated Discrete Circuit)modeling method and RON/ROFF modeling method are studied and improved in detail.Moreover,an FPGA resources optimization method based on Signal-to-Noise Ratio(SNR)was proposed.This thesis has completed the following work:(1)This paper takes the three-phase inverter with LC filter as an example to analyze ADC modeling method and RON/ROFF modeling method in detail.For the switching oscillation problem in ADC modeling,an ADC parameter optimization method is proposed to improve the model accuracy.For the problem that RON/ROFF variable system matrix is large and takes up too much FPGA resources,RON/ROFF decoupling modeling method is proposed.The two methods are verified by offline simulation respectively.Finally,the characteristics and applications of ADC modeling method and RON/ROFF modeling method are compared in detail.(2)The quantitative calculation method of model precision based on SNR is proposed.Firstly,the basic concepts of quantization error and SNR are introduced.The model precision is quantitatively described by SNR.Combined with the modeling process of the power electronic converter,the relationship between bit-length,quantization error,and SNR is analyzed.Furthermore,the quantization error formulas of coefficients,input signals,and multiplication operations are derived.It provides a theoretical basis for FPGA resource optimization of HIL real-time simulation in the next step.(3)FPGA resource optimization method based on SNR is proposed.Combined with power electronic converter modeling,the above mentioned SNR calculation is extended to matrix operation,and the relationship between time step,discretization,and SNR is analyzed in detail.Through quantitatively calculating the influence of the bit-length,time step on the model accuracy,and the minimum bit-length and time step that satisfy the model accuracy are chosen to save the FPGA resources.Taking three-phase inverter with LC filter as an example,the FPGA resource optimization method is applied to ADC modeling and RON/ROFF modeling respectively,and the offline simulation results can verify the SNR theory.(4)For ADC modeling and RON/ROFF modeling method,the Vivado HLS(VHLS)-based HIL real-time simulation of the three-phase inverter with LC filter is completed respectively,and another VHLS-based HIL real-time simulation case of a multi-switch TNPC(T-type Neutral Point Clamped)circuit is also presented.The experimental results show the validity of the improved ADC modeling and RON/ROFF modeling method,and the comparison results of FPGA resource consumption verify the rationality of the SNR theory.