Studies Of Single-Event Transient Layout Hardened Techniques And Verification Strategies Of Standard Cells

As the technology scales down and the clock frequency enhances, Single Event Transient (SET), instead of Single Event Upset (SEU), gradually becomes the dominating contributor to single event Soft Error Rate (SER).Layout hardened techniques and simulation verification strategies for SET of standard cells with 180nm bulk CMOS process have been proposed. The advanced radiation-hardened DSP, using these standard cells, accomplish good experiment results. The main works and contributions are listed as follows:â'ˆTCAD mixed-mode simulation results demonstrate that increasing the nwell contact width or decreasing the distance between the nwell contact and the drain of PMOS can significantly decrease the produced SET pulse width. However, for NMOS, the hardened effect on SET is not such remarkable as that in PMOS when doing the similar design. The results also indicate that for PMOS, the Body contact and the use of deep P+ well would enhance the bipolar amplification, and for NMOS, the use of deep N+ well would make the generated SET wider. The effect of the rectangular and finger gate layout on the produced SET pulse width are also studied, the results indicate that, for NMOS, SET produced in device with finger gate layout, is smaller than that produced in device with rectangular one. On the contrary, for PMOS, SET produced in device with finger gate layout represents to be wider. The source of NMOS is collecting electrons when the ion strikes at the drain, this decreases the charge collection of the drain and restrains the SET pulse, while the source of PMOS supplies holes and increases the charge collection of the drain, which makes the SET pulse become wider. Compared with the rectangular gate layout, the finger gate layout will enhance these source effects mentioned above, which gives an appropriate explanation to the results.â'‰The SET hardened effect of annular gate NMOS is investigated by TCAD simulation. We find that the SET pulse of the annular gate NMOS is smaller about 23% than that of the rectangular one, and it is also smaller than that of the annular source and the annular drain ones. The annular drain NMOS gets the widest SET pulse. Study of the charge collection and the potential under the source shows that the source collects electrons and the PN junction between the source and pwell is reverse-biased all the time, which indicates there is no bipolar amplification effect. The annular gate NMOS has the best SET mitigation characteristic owing to the source having the best effect on collecting the electrons and the drain having the smallest SET sensitive area.â'ŠThe evaluation and quantificational simulation methods are proposed to verify the SET hardened capability for both the combinational and sequential standard cells. The methods have been used in the whole standard cell library and show a better efficiency. â'‹The effect is introduced that the ion striking at an internal sensitive node of SEU Hardened DICE D filp-flop (DFF) when it is reading data would result in performance degradation or even an error. For DICE DFF, the sensitive nodes are found out and quantificational analysis is performed on those nodes.