| In recent years, power consumption has become a crucial constraint in designing microprocessor-based embedded systems that are fueled by the revolution in handheld mobile devices and the wide demand for intelligent appliances. Energy efficient design of these systems has become synonymous to enhancing system performance or reliability. Unfortunately, in general, high-performance reliable design requires large driving power budget. Moreover, the forms of dissipated power are evolving and most contemporary low-power optimization techniques are not necessarily orthogonal to system speed or trustworthiness. Recently, the focus of power dissipation in the new generations of microprocessors has shifted from dynamic to leakage, a previously irrelevant form of power loss that causes battery supply to drain and shutdown prematurely due to energy waste. The problem has been exacerbated by the aggressive process scaling; device level technique originally used by computer architects to conserve dissipation, enhance performance and reduces the sizes of increasingly condensed digital circuits.;This dissertation studies leakage power proliferation in the new generations of embedded cache memories. These types of memories are highly critical to performance, occupy relatively large silicon area and are by far the most power-dissipative entities within processor datapath. The work provides methods to amortize leakage dissipation, an area that is gradually becoming lucrative for research.;As a first contribution, this work devises a novel cache scheme called lethargic cache where storage cells are organized uniformly but differentially across its address space based on voltage-gating, an attractive circuit-level leakage minimization technique used to deactivate idle cells selectively. The organization adopts a state-preservative mechanism that exploits slacks within cache structures benefiting from temporal locality properties. Our results indicate that such a scheme successfully reconciles the costs and benefits of leakage reduction.;The second contribution involves developing an architectural leakage power framework where the threshold voltages of the cache basic cells are parameterized and used to project leakage power at early stages of design cycle. To achieve this, the work integrates various homogeneous modules into an existing cache power and time estimator. The resulting framework serves as an advanced leakage quantization tool and allows for more design exploration.;As a third contribution, the dissertation studies the short-channel transistor theory and thoroughly investigates the merits of continually minimizing the length of the conduction channel as a measure of power optimization. The associated second order effects in terms of performance, susceptibility to noise and silicon area are also investigated. |
