Design Of Distributed Interpolative Sigma-Delta Modulator

Based on the analysis of SigmaDelta modulator processing principle, performance, structure characteristics and circuit implement, this thesis completes the design of fourth-order feedforword interpolative SigmaDelta modulator. The key blocks include integrator, feedforword summation circuit, local feedback, quantizer, et al. The system design and simulation are accomplished in MATLAB, the circuit implementation and simulation are completed in Candecne.Conventional SigmaDelta modulator structure basically are single-loop cascaded integrators and MASH. Because of implement in analog circuit and high order noise shaping, single-loop high-order modulation is adopted in this thesis. The feedforword summation loop structure can reduce the linearity overload in integrators and the swing of integration signals. Input signal feedforword branch will transfer the signal directly to quantizer, ensuring the unity gain of signal transfer function and simpleness of noise transfer function. Local feedback branch can realize the NTF zero optimization and enhance noise shaping performance within signal band. The system design is completed in MATLAB, and the performance is 106.4dB SNR, 17bits ENOB under 128 over sampling ratio, -6dBFS input signal.There are two methods to realize SigmaDelta modulation circuit, contiunous-time circuit and discrete-time circuit. On the consideration of SigmaDelta modulator requirements of capacitor accuracy and sampled signal process, this thesis adopted switched-capacitor circuit technique to accomplish analog circuit realization. Feedforword summation and local feedback are implemented in capacitor network. 1-bit quantizer is realized by a dynamic comparator with latch. Cascaded integrators have non-inverting input. The whole circuit is controlled by non-overlapping clock signals. In Candence simulation environment, the modulator circuit is completed in 0.5μm CMOS parameters and simulated in time-domain. The output is 103dB SNR and 16.8bits ENOB in -8dBFS input signal, no overload discovered. The result satisfies expectation.