The Research And Implementation Of High Performance Vector FMAC Unit For LTE

YHFT-Matrix is a high performance vector DSP designed by National University of Defense Technology (NUDT). It is mainly used for the application of wireless communication basestation of LTE, also promising in the domain of image, radar signal and sonar processing. Its VLIW architecture can issue 10 instructions at most and work at 500MHz, its peak performance can be up to 5000MIPS which will support the main wireless communication agreements of LTE, LTE-Advanced and WiMAX effectively.In order to research and design a high performance vector floating-point multiply accumulate (FMAC) unit for LTE, the characteristic of the architectures of advanced DSPs for LTE were studied in this thesis, and the requirements of FMAC operations and main architectures were analyzed. Furthermore, the kernel arithmetic of LTE was analyzed and mapped by VLSI implementation. According to these, in order to support quick arithmetic of LTE, the architecture of vector FMAC unit which includes 16 isomorphic vector operating units containing a FMAC part supporting floating-point MAC operations of double-precision and paired single-precision was proposed.In addition, based on the low delay fused multiply-add configuration, a power- efficient five-staged FMAC pipeline was designed and implemented. And we analyzed the critical path of FMAC particularly, then we partitioned it to five stages to fit 500MHz frequency. Also, we researched and implemented the hardware reuse technique for kernel operation units of FMAC to support 3-cycle double-precision and paired single-precision floating-point multiplier, 5-cycle double-precision and paired single-precision FMAC, 5-cycle paired single-precision floating-point multiplier and add the product, and 5-cycle single-precision floating-point complex multiplier.Finally, we have made a systemic simulation verification and coverage rate analysis of RTL description of FMAC, and the result shows that the verification covers every function unit and most floating-point operating boundary. Furthermore, we have optimized the logic delay of FMAC in many ways and synthesized it in TSMC 65nm CMOS technology by Design Complier of Synopsys, and the result shows that its frequency can reach 500MHz, the power is 32.23mW and the area is 241740.5um~2, which outperform the traditional low delay FMAC structure.When working at 500MHz, the peak performance of the proposed vector FMAC unit can reach 16GFMAC for single-precision, 8GFMAC for double-precision and 4GFMAC for single-precision floating-point complex multiplier, these show that the proposed vector FMAC unit will entirely meet the high requirements of LTE.