Digitally Trimmable Analog Front-End Chip Design For EEG Signal Acquisition

There is a growing demand for health care now, and those traditional electroencephalogram (EEG) measurement instrumentations no longer meet the requirements on convenience and reliability. Patients need portable biopotential acquisition systems for long-time monitoring in order to obtain more accurate diagnostic messages. The rapid development of integrated circuits technology paved the way for developing a smaller, low noise, low power portable biopotential acquisition system. And analog readout front-end block is a critical block for biopotential acquisition systems. The main purpose of my thesis is to study the design method of low power, low noise analog front-end (AFE). Based on this, a multi-channel AFE chip for EEG signal acquisition can be designed.Firstly, my thesis introduces the biopotential signals briefly. Then, the general framework of biopotential acquisition system is introduced from the view of the system. We summarize the difficulties and solutions of AFE design in system, and finally present the design specifications. Then this thesis studies the low noise amplifier design method, and presents the circuit design of each module in the EEG acquisition chip. Finally, the simulation results and layout design of the chip are given.The chip is designed using a TSMC 0.18μm 1P6M CMOS process. The supply voltage is 1.8V. Post-layout simulation shows the current consumption of one channel is 700nA, the input referred noise is 2.2μVrms from 0.1Hz to 360Hz, and NEF is 3.54. The gain is 3-bit programmable from 54.2dB to 72.3dB and the high cutoff frequency can be adjusted using 3 bits from 152Hz to 360Hz. It has been shown that this low-noise, low-power AFE is suitable for a portable EEG acquisition device.