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Logic Design And FPGA Implementation Of 10 Gigabit Ethernet TCP/IP

Posted on:2017-02-10Degree:MasterType:Thesis
Country:ChinaCandidate:Z H ChengFull Text:PDF
GTID:2308330488485623Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
The 10G Ethernet & TCP/IP technology is driving the rapid development in the field of distributed data acquisition, however, the commercial 10G network interface card is severely limited, so the implementation of 10G Ethernet TCP/IP based on the FPGA has become the inevitable trend. Subject to the complexity of the TCP/IP and the processing difficulty of high data throughput rate, lightweight protocol stack is used in most applications, which avoids the complicated design problem of transmission control protocol. In order to solving this problem, this thesis implements the logical design of 10G Ethernet TCP/IP based on FPGA, not only achieving high transmission rate, but also ensuring the high reliability and flexibility.This thesis firstly introduces the TCP/IP protocol suite, and then further discusses three key technologies:sliding window mechanism, timeout-retransmission algorithm and slow start method, and finally clarifies the nature of TCP reliability. For the design of 10G Ethernet TCP server, this thesis puts forward the parse-control-assemble conception. The protocol parse part provides an improved IP header checksum algorithm, which can parse the received Ethernet packets at high speed. The protocol control part adopts the timeout and retransmission technology to ensuring the reliability of TCP, and keeps the data block flowing at high speed by using the sliding window mechanism, and avoids the TCP start up congestion with slow start method. The protocol assemble part arbitrates the priority of different types of the outbound packets, ensuring that the packets are transmitted without conflict.Given the particularity of TCP connection-oriented, this thesis proposes a simulation method to imitate the behavior of TCP client by using the TCP client outbound packets as excitation, which have been captured by the Wireshark software. The comprehensive simulation of TCP server is successful. The 10G network testing platform is set up, completing the tests which include ARP reply, ICMP echo reply, TCP connection establish, TCP data transmit and receive, TCP connection termination. The instability of network is imitated by the clumsy software, during which the timeout-retransmission and retransmission recovery process is successfully observed, and the timeout-retransmission function has been implemented.Finally, This thesis comes up with a method of measuring the real TCP transmission rate, and introduces the concept of mean and variance to evaluate the TCP transmission rate and stability accurately. Test results show that the transmission performance of 10G Ethernet TCP/IP logical design is up to 4000Mbps, which fully satisfies the application of the distributed data acquisition system.
Keywords/Search Tags:Distributed Data Acquisition, 10G Ethernet, TCP/IP, Sliding Window, Timeout-retransmission, Slow Start
PDF Full Text Request
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