SOC Design For Frequency Conversion Control Chip

In view of the current domestic research status of the frequency conversion control chip, designed a new frequency conversion control chip with independent intellectual property rights, with independent system architecture, with strong commonality. The design and implementation of the SOC chip reflects that designer had a beneficial exploration in chip design methodology and architecture.This paper introduced the overall framework and the whole process of variable frequency control chip SOC, including the design and implementation of each module in the RTL design, logic synthesis, low power design, testability design, layout design and the whole SOC chip equivalence checking.In this paper, my work mainly focus on four Points. The first is to introduces the SOC chip design methodology and IP multiplexing technique and, on this basis, proposes the framework of frequency conversion control SOC chip, completing the function definition, module partition, CPU choosing and ruling and bus types selection. The second point is to expound the main IP logic design, physical design and the method of hardcore embedded into the whole SOC. In the logical design, an IP RTL description and function simulation are completed. In the physical design, the paper detailedly describes the IP core's space, power pins and the simulation of territory. The third point is to introduce the whole SOC chip level design, including the power introduction, pad options and the layout of hard macro, etc. Finally, analysis and verification on the whole SOC chip are finished, such as function simulation, static timing analysis and equivalence checking, etc.The paper uses the complete set of Synopsys company's ASIC Design tools and adopts the top-down Design method. RTL description in all of the modules is realized by Verilog HDL, logic synthesis is completed through Design Compiler tools, measurability Design is accomplished by DFT Compiler, layout Design is used by IC Compiler and finally equivalence checking is finished by Conformal. The main contribution of the paper is to provide a complete design proposal for SOC chip, including IP core design, the design of SOC chip and IP multiplexing technique, and solve many difficult problems for chip design process, such as SOC chip basic framework and collaborative work between each module, code cropping of SOC core processing module, OR1200, asynchronous-circuit design between each module interface and layout plan for IP core embedded SOC chip, etc. This SOC chip not only realize specific frequency conversion control output, but also according to software program written by engineer distribute registers and realize to control input signal acquisition and frequency signal output. It is universal and flexibile. This design is to provide a configurable SOC chip for realize functions, and general IP core between chips.