A 10-bit Successive Approximation Adc Design

With modern communication systems, portable electronics, consumer electronics a nd automotive applications of continuous development of the system-level SOC chip into the mainstream of the current market. High-performance, low power, low -cost embedded ADC becomes an important direction of development. ADC as the embedded peripherals with other analog circuits and DSP cores integrate on a chip, so not only can save packaging and testing costs, but also enhance the reliability of the system.This paper summarizes the ADC embedded under the special requirements. Complete an embedded application of 10-bit, 3.3V, 2MHz successive approximation ADC design.Body structure in the system, introduces a large number of switch circuits between the comparator and DAC Control (DAC) section. Hhe circuit can work between work and power-saving mode, thereby reducing unnecessary power consumption. The overall structure is similar to the conventional successive approximation ADC, but also has unique features. Sample and Hold circuit built-in DAC saves circuit costs and chip area. The hybrid calibration DAC reduces the use of passive components and the matching requirements of precision, thus improving the accuracy of digital-analog conversion. To ensure the digit-al-analog conversion rate and linearity.In this paper, comparison of two successive realization of design ideas: first, the comparator input side is the same sample, while the other input is scaled in proportion to the reference voltage; Second, one of the comparator input is constant reference voltage, the other end is the input sample and the reference voltage after scaling the result of superposition. In order to reduce the DAC output voltage on the comparator input range requirements, bold use of capacitive pressure relief technique and ultimately to achieve the reference voltage to supply voltage. The introduction of high-precision design of the comparator output offset correction technique (OOS), and sampling phase offset correction phase and combined to reduce the difficulty of timing design.The circuit use Hspice and Matlab to system simulation and spectrum analysis. The results show that: the overall static power dissipation of ADC module is 3.16mW. The maximum sampling rate is 2MHZ. The maximum differential nonlinearity and integral nonlinearity meet the design requirements. The layout area of ADC is 0.69mm×1.23mm. This chip is designed in TSMC 0.18um single-poly six-metal standard CMOS process, and the test results meet the desired design requirements.