Along with the development of science and technology, non-linear, non-stationary signal processing is becoming an important challenge in the engineering practice and scientific application researches. The traditional Fourier analysis requires the system to be linear and the data to be strictly periodic or stationary. Therefore, Fourier analysis and such based on it : the short-time Fourier transform, Wigner-Ville distribution and wavelet transform analysis can not well analyse non-linear, non-stationary signal problem. Empirical Mode Decomposition (EMD) is a new approach analysing non-linear, non-stationary signals in the past decade . This method can make complex signal decomposed into a limited number of Intrinsic Mode Function (IMF), components of the IMF appled time-frequency distribution through the signal Hilbert transform. As so far, at home and abroad, the current method of EMD were largely confined to use in software applications. This subject is trying to integrate FPGA, SOPC technology to achieve EMD method. As the realization of EMD method, the process and the characteristics of FPGA and SOPC, this paper explored technical problems using C language programming to achieve EMD in SOPC embedded a Nios II CPU. The main contents are illustrated as follows:designed the system hardware structure and select the FPGA, off-chip SRAM and SDRAM, UART and on-chip RAM blocks according requirements,as well as set the parameters and builded SOPC hardware platform.implemented the EMD decomposition of the collected data by SOPC technology. Dealling with the signal edge effects by one Mirror linear estimation, implement the EMD decomposition of the data in on-chip RAM. The IMF components that gotten in the proceeds of the decomposition transmitted to PC via UART machine.the actual signal of the EMD decomposition, and compared the differences between the decomposition of the hardware and software,at last discusses the advantages and disadvantages of hardware decomposition... |