| In this paper, it firstly gives the background and technological roadmap. The technological roadmap is redefining the micro-architecture while keeping exactly the compatibility with traditional 8051 microprocessor to improve the performance. It then shows architecture design of instruction pipeline, including the double-shoot superscalar, the branch prediction and the dynamical execution. Then it shows the design of integer computing, logic and bit operation, memory access unit and branch unit. After it, the paging and virtual address based memory access unit design is given. Then, it gives in terms of verification flow and performance assessment, the process of co-defining the functional and verification document in the fist place, then RTL simulation to pass test coverage and coding-style check, then FPGA verification and final is the gate-level verification is adopted. The test coverage data is given in this section. And also in this section, the statistics on design bug accumulation shows that the design bug converged fast. Prior to FPGA verification, all severe bug and 99% other bugs have been fixed. The conclusion of the design is given in the last part of the paper.It shows that the design has been successfully taped out in Fujitsu Microelectronics 90nm process ASIC. The test indicates that it outperforms 30 times faster than its traditional counterpart under the same work clock frequency in execution commercial system software and the peak through output is two instructions per clock cycle. It is saying that the technological roadmap of the design is correct, the efficiency of pipeline is good and the capacity of Cache is enough. However, also in this part, it points out the performance will be hampered in case of work frequency is higher than 100MHz on account of no implementation of 3-hierachy memory and full-data-Cache. On the other hand, the constraint based automatic test vectors sequence generation should be also enhanced. |
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