Based On The PCI Express Channel Digital Receiver Design And Implementation

In modern electronic warfare, the electronic reconnaissance system need to accomplish the real-time searching, detecting, measurement, analysis, identification and direction finding of the radio signal. For the widely applications of frequency hopping communication, burst communication, adaptive communication, etc. and the increasing complexity of the electromagnetic environment, it is necessary to develop a type of digital receiver with high sensitivity, large dynamic range and high interception probability. In this dissertation, the theoretical analysis and the engineering implementation of such a multi-channel channelized digital receiver and its signal processing are introduced.The channelized digital receiver divides a board-band channel into multiple parallel-output narrow-band subchannels for the full interception probability by using a filter bank. For better performances of the reconnaissance system in detecting, recognition and direction finding of the signal, functions including a variable spectral resolution and the capacity of all-subchannels'data uplink are required in the digital receiver.The integration of multiple processing channels greatly decreases the physical size, power consumption and the cost of the system. Meanwhile it increases the consistency among channels. However, the output data of the receiver is greatly increased because of the real-time processing, increased requirement of the data rate and the integration of multiple channels.To solve the two problems mentioned above, the theories of software defined radio receiver, including AD and DDC basis, multi-rate signal processing and polyphase filter theory are studied; also, the derivation of the channelized processing model based on polyphase filtering is introduced in this dissertation. After the scheme design of the multi-channel channelized digital receiver with a variable spectral resolution, the implementation of the hardware platform is introduced, as well as the design and verification of the key-blocks which determine the functions and indices of the receiver. Those key-blocks include the test of the ENOB of the AD6645, high speed data transformation block based on PCI Express, functional design and implementation of the ISL5416, realization of the channelized processing block in FPGA.The final test result indicates that the hardware and all of the key-blocks accord with the request of the reconnaissance system in functions and indices.