Used To Guide The Interference Of Broadband Digital Channelized Receiver Research

Digital channelized receiver, which has the advantage of broadband instantaneous frequency coverage, simultaneous signal detection, good sensitivity and dynamic range, is one of the main research subjects of the radar intercept receiver. Broadband radar intercepter has recently become the inevitable trend of the development of radar countermeasure system. However, channelizer with wideband and large number of channels now faces the challenge of the real-time processing problem, the implementation of high order filter and FFT. With the rapid development of FPGA technology, it is possible to enhance the processing speed by using more resources. It is the starting point of this dissertation.A digital channelized receiver used for jammer guide, includes not only channelizer, but also high speed data acquisition and storage, high accuracy parameter estimation, central control unit, and jam guide part. All these parts influence each other. Supported by two corresponding programs, the implementation of some part of the system is also studied systematically.The main contributions of the dissertation are summarized as follows:1. The theoretical foundation of the channelized receiver, the multi-rate signal processing technology is introduced firstly. Two typical channelised architecture—the polyphase DFT filter banks, and the tree-structured filter banks are introduced.2. Aim to solve the wide-band channelizer real-time processing problem, the solution under the limited resource condition is summarized. A parallel architecture based on the unfolding of the poly-phase DFT filter banks is proposed under the full resource condition. It increases the channelizer throughput by the simultaneous work of the multi-processors and the improvement of the system clock. It guarantees the whole coverage of the time domain and the frequency domain of the wide-band signals. Our dissertation also presents the design, implementation and optimization of the architecture on FPGA. Simulation proves the good performance and feasibility.3. A radar intercept & jammer system which applies the wide-band digital channelized receiver is presented. Hardware specification and system function specification are also introduced. The flow of the channlised parameter estimation channel is explained briefly.4. The implementation of the fast interfere guide channel is finished. Test results from the experimental stage show that this receiver has excellent performance which guarantees the jammer system work validly.