Study On Real-time Processing Of Spectral Image Based On FPGA

In this thesis,the pipeline design and parallel processing in FPGA were studied,and the design flow of Vivado HLS was introduced in detail,the ability and method of image processing were analyzed based on the experiment.Vivado HLS is an instrument,which convert the signal or digital processing model built by C/C++/System C into RTL level model.HLS can greatly improve the design efficiency of FPGA,and accelerate the application in the field of high performance signal and data real-time processing.An accelerator with AXI4-Lite interface for a Zynq Processor Design was designed based on the synthesis,simulationand implementation process.The design optimization was realized through the scheduling and binding mode of HLS,and Vivado IP was created.According to the Verilog code generated in the synthesis process,the testbench was compiled,and the correctness of the design was verified,the analysis of the system performance was completed.The flame detection algorithm has been compiled,completed the reading and calibration of the four spectral single frame flame image,and made the correct detection according to the threshold set in the algorithm.The C code was converted into RTL level simulation by using Vivado HLS.With the flam detection algorithm as the application object implemented by C langurage,the comprehensive strategy of resources priority and speed priority were respectively achieved by using Vivado HLS,and the results of the implementation of the two comprehensive strategies were compared with the result of DSP.This thesis makes an investigates attempt in designing the IP of hardware accelerator and detecting the flame in the image based on the design process and optimization of HLS,which has a positive significance for FPGA platform in the design of real-time image processing.