FPGA Design And Implementation Of None-uniform Broadband Digital Channelizer

As a key component in satellite mobile communication system,the on-board processing of sub-channel separation,sub-channel switching and sub-channel reconstruction,as well as the exchange of both uniform and non-uniform bandwidth signal can be realized by non-uniform bandwidth digital channelizer.This thesis focuses on the study of the efficient implementation of the non-uniform bandwidth digital channelizer,which cosumes less hardware resources while ensuring the system function and performance.The main work of this thesis is summarized as follows:1.The polyphase decomposition structure and complex exponential modulated filter bank are studied.On this basis,an efficient implementation structure of non-uniform bandwidth digital channelizer is proposed,which can accurately extract the uplink narrowband signals and reconstruct the required downlink signals.This architecture has a low implementation complexity.2.According to the efficient implementation structure of non-uniform bandwidth digital channelizer,the system framework of non-uniform bandwidth digital channelizer is determined,and the appropriate hardware platform and system working clock are selected according to its system parameter index.The design method of the prototype filter in the digital channelizer is studied.At the same time,considering the resource limitation of the chip,a filter design method combining the frequency sampling method and window function method is adopted.Larger stop-band attenuation and smaller pass-band jitter prototype filter minimizes the order of the filter while ensuring that the system metrics are met.3.Based on the principle of modularization design,the non-uniform bandwidth digital channelizer system is divided into several modules,and then the FPGA design and function simulation of each sub-module is completed on the Xilinx ISE14.7 simulation platform.Finally,the whole non-uniform bandwidth digital channelizer is simulated functionally and analized.4.The board-level debugging of the non-uniform bandwidth digital channelizer is implemented.Translation,mapping,layout and other operations are completed in the ISE simulation platform,and then the hardware program is downloaded through the JTAG,which finally achieving the non-uniform bandwidth digital channelizer system on the FPGA hardware platform.Finally,the function and performance of the system are verified by testing.