Fpga-based High-speed Serial Transmission Technology And Realization

With the rapid development of the science and technology,the wider bandwidth transmission is required.It becomes the highlight in the industry.And then the high speed serial transmission technology appeared.Using this technology,the engineer can get the effect which was never made before.In fact,this technology has been accepted and utilized in many aspects,such as Serial RapidIO standard used in DSP, OBSAI and CPRI standards used in wireless and PCI-Express,Ethernet, Serial ATA,USB3 standards.Anyhow,the high speed serial transmission technology is becoming the new trend now.This paper is going to realize a typical high speed serial transmission on hardware,10G Ethernet PHY layer-10G BASES-X standard.Ethernet is a protocol which has a long history and after long time development,it has become one of the most widely used protocols in networking.The 10G Ethernet PHY layer consists of two Ethernet standard interfaces.One interface is the XAUI interface.It is at PHY layer which is combined by 4 high speed serial transmission modules.Every module has 3.125G line rate.They are channel bonding together.Because of 8B10B coding used,4 channels totally have lOGbps bandwidth.Another interface is the standard Ethernet XGMⅡinterface. It can be connected to 10G Ethernet MAC directly.To realize this meaningful high speed transmission design,the paper not only studies the high speed serial transmission technology, but also uses FPGA as the platform to do the hardware and software design.FPGA is cheap and easy to use.It is also very flexible.FPGA not only provides high speed serial transmission hard core,but also has lots of logic and registers resources.The engineer can use them to realize any design.The engineer can use the high speed serial transmission module in FPGA which has many settings to realize the different designs.This paper is to use FPGA to realize 10G Ethernet design,including software simulation and hardware verification.