Research On ROCKET I/O Based High Speed Data Transmission Systerm

In the real word, signals is continuous in nature, and multi-channel converters areoften required to sample large arrays of data and transmit them to FPGA for processingin data acquisition systems. As the ablility of computer data processing and the clockfrequency of system are promoted, the increasement of data transmission bandwidthhas become a key technology to improve the performance of complex data acquisitionsystem.Unidirectional high-speed serial transmission between multi-channelanalog-to-digital converters and FPGA is discussed in this paper. It is designed andimplemented with RocketI/O GTX transceiver embedded in Xilinx Virtex-5FPGA asthe physical layer based on a data acquisition and processing system for the designplatform. The design of data transmission layer and data link layer is discussed indetail. Furthermore, the method of FPGA implementation of custom protocol and theparameter configuration of RocketI/O GTX transceiver are presented. Also theexperimental results of timing simulation and hardware debugging in the ISEenvironment show that the quad-channel serial transmission is stable and right whenthe system reference clock is250MHz, single-channel serial speed is4Gb/s. The keytechnology of board-level design of high speed analog-to-digital converter and FPGAinterconnect is introduced in the end.In addition, this paper also discusses the implement method of image fusionalgorithm by using programmable logic device. The design method of image fusion IPsoft core based on weighed fusion algorithm using hardware description language isintroduced in detail. The image fusion IP soft core is packaged using ISE. Intellectualproperty rights can be protected by using IP soft core. The image fusion IP core is notonly reusable, but also can lay a firm foundation for the further development of imagefusion IP core library.