A Low Dielectric Constant Film On The Device Packaging Process And Packaging Process Optimization

Currently,it is very faster progress of IC industry,and especially for SB and NB chipsets of PC mainboard and high speed video chips.When chips vendors issue new device,they always emphasize new material implement for advanced technology shown.As a semiconductor assembly process engineer,do know the technology relativity between wafer manufacture with chip assembly.So,we need to well understand new material and process in wafer manufacture in time.At the same time,also need to think about and find out overall solutions for it to avoid progress delay of assembly technology.Now,there are more and more quality issues for low k wafer productions in most of assembly factories and it lead to low yield,then efficiency and cost loss accordingly.There are two major defect modes,chipping on wafer saw module and peeling on chip wire bonding module.ASE(Shanghai) assembly and test LTD.belongs to ASE group and is the biggest professional semiconductor assembly and test factory in global,and built up in Pudong Zhangjiang high-technology zone in 2002.Their production package covers QFP,BGA,MCM and SIP.Currently,with low k material phased in by end customer and lab foundry(SMIC,GSMC and TSMC),it will push us to speed up improvement for low k wafer assembly.As a leader of assembly process in ASE,I coordinate all team members of each process engineer to involve the further study of process optimizing with related department great support.The key points in the paper will focus on two process modules which impacted by low k material,wafer saw and wire bonding, and will investigate to find out total solutions thru analysis for process method, machine capability,assembly material and parameter setting.And I also hope that it will be some helpful for feasibility study and problem solving about low k assembly in local companies.