Analysis On Defect And Improvement Of Re-liability For QFN Cu Wire Bonding Based On Low K Dielectric Layer

As the price of gold continues to rise globally, the inflated cost of’gold wire already cant satisfy the expectations of the assembly packagingOEM clients. Therefore, the new material, a low cost alternative source,copper wire started to enter the packaging industry gradually since2000.After the financial crisis in2009, the semiconductor products are gettingcheaper and cheaper than ever before. Following up this trend, the neces?sity for IC assembly industry to develop low-cost packaging technology tofeed the high-volume loading demand is becoming higher and higher.Therefore, copper wire has been considered to replace gold wire as thebonding material, especially in some fine pad pitch products, as it has bet?ter reliability in high accelerated stress test.In recent years, many domestic or oversea researches are de-velopingthe merit of copper and Pd/copper alloy as wire bond material. Comparingwith gold wire bonding, copper wire gains the advantages of lower cost,better electrical properties, outstanding thermal-electrical effect, and per?fect reliability performances. However, after the launch of90nm Si nodetechnology, with the wide application of low K dielectric and copper metallayer, TaN/Ta barrier layer is configured into IC manufacturing with90nmtechnology, the risk of copper wire injury on bonding pads become moreserious than before. The substances in the layer between the low dielectricconstant material and the corresponding low adhesive strength material aswell as the inter layer dielectrics(ILD)-Copper stacking process lead togreater risk of pads damage during copper wire bonding process. However,the inherent fragile attribute of the low K materials, the poor adhesion be- tween the wafer interlayers, the more severe wire bonding parameters(such as the higher ofrce, higher power and higher temperature) corre?sponding to the higher mechanical strength and hardness of the copperwire than gold, along with the enhanced hardness due to the oxidation onthe surface of the Cu balls during electronic ignition, all these factorsmen-tioned above makes the cratering occur on the bond pad more fre?quently. As for the fragile Low K medium chips, crateirng will be accom?panied by cracks of the ILD layer, which will cause electrical functionalfailure due to circuit short or circuit open. Therefore, copper wire bondingbecomes the biggest challenge in the packaging industry. It requires morerigorous study on this project for improvements.We are going through two major aspects to optimize and enhance theILD crack. On one hand, concluding merit and demerit through analysis ofthe structure of different bond pads will optimize the ILD layer in the innerstructure. On the other hand, we should find out the best parmieter to op?timize the copper wire bonding. This paper generates the design of copperwire bonding experiment for QFN package on the chip with55nm low Ktechnology. The main research is to perform analysis of low K dielectricbonding defects. The direction is improving the defects and achievinghigher yield performance based on better understanding of the inherentcharacteirstics of copper material, inert gas and wafer chip technology de?sign rules.The direction of thesis is to analyze characteristics of wire bonding en?vironment and the design of bond pads structure to minimize the probabil?ity of damaged pads with the best material and optimized bonding param?eter.In terms of the method for improving defects, parameter op-timizationfor copper wire bonding is an effective one. However, to implement thismethod successfully, it requires proper material as well as more stable andreliable environment to maximize the advantages in full. This thesis fo?cuses on the following aspects to carry out the research:1) Based on the existing process conditions to analyze material properties and the bondingenvironment characteirstics step by step;2) According to the characteris?tics of the wafer manufacturing process, generating the wire bonding paddesign method based on large amounts of data research;3) Based on thecurrent wafer manufacturing process, finding out the most optimal processparameter through design of experiment with the method of process opti?mization;4) In the process optimization process, verifying the reliabilityand operability through moisture aging test;5) Performing final validationthrough mass production after process parameter optimization to obtain astable process, implementing it into further mass production and eventuallyachieving higher yield performance.