Key Technologies Based On The Eigenspace Of Target Recognition Method In The Fpga

Radar target recognition is an important developing field of modern radar technology. Radar technology is being mature, which makes it to be practical. In the dissertation, FPGA implementation of a single float-point SVD processor is researched, which is a key design for the eigen-subspace extraction algorithm using Singular Value Decomposition (SVD). In the limitation of resources on FPGA, the dissertation researchs the inplementation of processor by high-speed and exact numerical precision. the serval architectures of key computation unit are presented, and the basic computation unit and transmission rule of matrix are improved. These architectures are compared and analyzed in detail in terms of speed, area and numerical precision by simulation. Finally the architecture of processor which is consided by its performance and optimization design is presented, and the performance of this SVD processor is validated by simulation. The main contributions of this dissertation are as follows:1. The eigen-subspace extraction algorithm using Singular Value Decomposition is discussed. Three methods which compute SVD on FPGA are studied, including Two-sided Jacobi Algorithm, the array architecture called BLV and the parallel transmission rule of matrix;2. In order to satisfy the performance of area, high-speed and exact numerical precision, two algorithms called conventional CORDIC algorithm and modified CORDIC algorithm based Greedy Agorithm (GA) are discussed. The scale factor of modified CORDIC algorithm is variable, the design solves the problem. Meanwhile, a single float-point adder/subtracter is implemented in the design;3. The designs of two key computation units are presented in this dissertation. In the angle unit, the design improves the performance by Look Up Table (LUT). In the rotation uint, the Two Plane Rotation method is used to design it. In the disseration, serval designs for the rotation uint are presented to implement on FPGA in detail;4. The entire architecture of a single float-point SVD processor is presented in this dissertation. The disseration introduces the designs of all of modules in SVD processor in detail. The design in this dissertation improves the parallel transmission rule of matrix to introduce an efficient method to achieve the element transmission. For the key computation unit, the designs make use of the above architectures and parallel basic modules to implement. The performances of 4×4 matrix used above architectures are compared and analyzed in terms of speed, area and numerical precision;5. An efficient method called an estimated sin/cos method is introduced to achieve the SVD processor design to decrease the areas and improve the performance on FPGA. The design of a single float-point SVD processor is achieved by this method and the resources and speed are optimized and above entire architecture. The simulation validates the performance of this SVD processor.