| The demand for a mobile device to support multiple wireless standards, such as GSM, WCDMA, HSDPA, Wireless LAN and WiMAX, and to offer features such as seamless mobility, higher data rates and data intensive multi-media applications, has gathered momentum in the last decade. Existing solutions lack flexibility, scalability and adaptability to accommodate the requirements of the future wireless standards. Furthermore, current solutions are not power efficient and cannot deliver necessary computational throughput. A study and survey of the computational requirements of the wireless standards is carried out to determine most frequent operations and similar algorithms across different wireless standards. A heterogeneous and programmable multi-processor platform is proposed to support the computational requirement of wireless standards, which also addresses scalability, flexibility to the future standards. The proposed multi-processor platform contains a network of programmable radio processor (PRP) elements. Each PRP contains multiple SIMD processing cores with communication algorithm specific instruction accelerators. The main focus of this thesis work is to develop a 128-bit SIMD based application specific processor (ASIP) core with CORDIC instruction accelerators. A hardware efficient sub-word parallel complex multiplier and accumulator (CMAC) is developed. It is also the purpose of this work to reuse the execution units of the SIMD processor in mapping new instruction accelerators. By reusing the hardware of designed sub-word parallel CMAC for CORDIC instructions, four iterations of CORDIC algorithm are mapped onto the hard ware of CMAC. Hardware implementation of the proposed ASIP is carried using Verilog HDL, and the synthesized model of the processor execution units is obtained from Synopsys design compiler. Timing and area analysis of the processor execution units is performed using Primetime tool. Lastly, an application of the developed CORDIC instructions in QR decomposition and OFDM based channel equalization algorithms is demonstrated. |
