.4-bit Risc Mcu Ip Soft Core Design Studies

This topic research goal is to develop and design a 4-bit RISC MCU IP cores. After investigation and comparison on the market, through synthesis on the concrete function, application characteristic and hardware demand of kinds of domestic electric appliances class products, CPU architecture and common used peripheral hardware are confirmed as the basis research, in order to design series products based on the design.After the thorough careful research, Harvard Architecture which the data bus and the instruction bus were mutually separated, as well as two-pipeline architecture of Microchip technical company's PIC microcontroller is finally accepted. The instruction set is mainly referred to the PIC instruction architecture, and is unified with own hardware characteristic to carry on the design. During the design, the system architecture, instruction system and system timing of PIC and other well-known series MCU were analyzed firstly, and then the entire MCU core was partitioned with a top-down methodology that systematically partitions a complex design into smaller functional units that can be designed and verified individually and more easily. A feasible RISC MCU IP module was built. All modules were achieved by using Verilog HDL and IP core technology, simulated, synthesized and verified with some EDA tools.The designed IP core mainly includes the CPU basic module, the periphery commonly used basic module and the MCU interruption system. This article emphatically discusses the working principle and design method of each CPU basic module through the process of the CPU pipeline, then approximately introduces the periphery commonly used basic module, finally carries on the detailed description on the MCU interruption system. The overall system has already passed the comprehensive instruction set test, including single instruction collection test and instruction combination test. The results showed that the MCU IP core can correctly execute all instructions except for stop and wait, and meet the performance of the MCU we designed.