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Based On The Cmos Process, The Rf Power Amplifier Design

Posted on:2009-11-18Degree:MasterType:Thesis
Country:ChinaCandidate:H Y YuFull Text:PDF
GTID:2208360245479194Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
This paper presents the design of Power Amplifer,the key component in the end of RF transmitter.According to the Wireless LAN 802.11a standard,the Power Amplifier is designed and simulated with the ADS circuit simulation software of Agilent.First of all,on the basis of analyzing power amplifier's structure,design principle and performance,according to the application of power amplifier background,select the Class A amplifier to design.By applying synthesizing a number of factors,select third-stage differential amplifier of cascode structure and co-source structure reasonably,to distribute gain and output power.Then use ADS software to design,optimize and simulate.The simulation results are:under the conditions of 1.8 V supply voltage,the output power Pout is up to 21.7 dBm at P1dB compression point,saturated power output is about 23.5 dBm.at 5.2 GHz.positive transmission coefficient S21 reaches 25.4 dB,the output point of third-stage intermodulation is about 29.5 dBm.The Power-Added Efficiency PAE is about 29%at saturation point.Static work current is about 810 mA.The output results show that the power amplifier in the frequency range has absolute stability,reaches a very good input and output match,obtains good linearity and isolation,the ultimate simulation results meet 802.(?)a standard.Secondly,aim to low efficiency,low integration and more stages of the third-stage Power Amplifier,a second-stage Power Amplifier is bring forward to ameliorate these shortcomings,The measurements includes the design of passive spiral inductor,rational use of Cascode inductors,improving the bias circuit design.The simulation results are:the output power Pout is 18 dBm in P1dB point,in the condition of input and output match,the power gain is 30 dB at 5.2 GHz,the PAE at 1dB compression point is 16%,the output of IP3 is 26.8 dBm,the total static work current is about 252 mA.These results indicate that the performance of improved Power Amplifier meets the design requirements.Finally,execute the design of layout.According to the characteristics of CMOS technology in Deep Submicron,by using TSMC 0.18μm CMOS technology library and Cadence software,draw the layout of the Power Amplifier circuits that have been completing design and simulation.These above jobs have certain value to the work of the RF circuit design.
Keywords/Search Tags:Wireless LAN. Power Amplifier, CMOS Technology, Layout Design, ADS Simulation
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