Development of integrated RF CMOS power amplifiers for wireless communications

This research is dedicated to the development of monolithic-integrated RF power amplifiers in CMOS technology. The input and output of the amplifier are matched to 50 Ω with on-chip inductors and capacitors. There are two prerequisites for the amplifier design: high-Q on-chip inductors and good RF MOSFET models. The spiral inductors are the most popular on-chip inductors. Because of the limit of technology, the Qs of the spiral inductors in CMOS technology are very low, typically less than 5. The first section of the research focuses on the Q-enhancement of spiral inductors on Si. A novel implementation of the patterned ground shield technique is proposed to effectively mitigate the inductor loss through the substrate. The effects of metalization in Si IC technology on the Qs of spiral inductors are studied with EM simulations. To obtain the accurate prediction of RF performance, good device models are required. Although the BSIM3v3 model has been widely used in industry to model the submicron MOSFETs, the BSIM3v3 model is still incapable of presenting the RF characteristics of MOSFETs. For RF power amplifier design, the transistor model should include the large-signal characteristics of the transistor as well. A new BSIM3v3 RF model is developed for both small-signal and large signal RF circuit simulation. Finally, the first 3-V 1.9 GHz monolithic-integrated CMOS power amplifier is developed.